This invention is directed to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a method of forming an insulating isolation layer in a semiconductor device.
In the manufacture a bipolar semiconductor integrated circuit devices, efforts have been made in the fabrication of isolation layers or regions in various devices to increase the density of the integrated circuits by adopting an insulating isolation of V-groove structure which has the merits of decreasing the area which is exclusively occupied by the isolation layer prepared in accordance with the known art and of eliminating adverse effects in the performance of devices where the isolation layer and the functional layer of the device are arranged close to each other.
An example of the known insulating isolation layer of the V-groove structure is shown in cross-sectional view in FIG. 1. In a silicon substrate of a two layer structure comprising an n-type silicon epitaxial layer 2 formed on a p-type silicon substrate 1, there is formed the V-groove 4 with its surface covered with a silicon dioxide (SiO.sub.2) film 3 penetrating through the n-type silicon layer 2 into the p-type silicon substrate 1. High purity polycrystalline silicon having a high specific resistance is filled into the V-groove, and a thick silicon dioxide (SiO.sub.2) film 3' which is usually 5 to 6 .mu.m wide is formed on the protruding surface of polycrystalline silicon 5. An insulating film 6 on the surface of the n-type silicon layer 2.
Although this known insulating isolation layer is formed of polycrystalline silicon, the layer has been used only for the purpose of insulating isolation and for no other purposes whatever. Attempts were made to confer electric conductivity to the polycrystalline silicon in the V-groove which occupies considerable area of the substrate and to utilize the insulating isolation layer as part of wiring layers interconnecting the electrodes with a view to further increasing the integration density.
However, in various methods proposed to fill the V-groove 4 of the structure as shown in FIG. 1, of which the internal surface is covered with the SiO.sub.2 film 3, with an n-type or p-type electrically conductive polycrystalline silicon by means of chemical vapor-phase deposition (CVD), many technical problems had to be coped with due to the facts that the electrically conductive polycrystalline silicon in the V-groove runs continuously throughout the entire surface of the substrate, that the specific resistance of the polycrystalline silicon layer cannot be made so low, that the isolation of devices becomes incomplete when a high electric potential is applied to the polycrystalline silicon layer due to the formation of a channel in the metal-oxide-semiconductor (MOS) fashion in the p-type silicon substrate around the edge of the V-groove, and the fact that SiO.sub.2 film interposed between the polycrystalline silicon layer and the silicon layer of the substrate is relatively thin. An attempt to positively utilize the insulating isolation layer as a wiring layer interconnecting the electrodes has not been practiced in manufacturing bipolar integrated circuit devices.